(1) Field of the Invention
The present invention relates to a step-down circuit, which is mounted on, for example, semiconductor integrated circuits, for stepping down the power supply voltage.
(2) Description of Related Art
Recently, minute processing for higher density integration of LSI (Large Scale Integration) has been progressing. As the higher integration progresses, the withstand voltage of transistor decreases; and thus, it is getting difficult to increase the power supply voltage.
On the other hand, depending on the purpose, there is such a case that, due to the system power supply, the power supply voltage is high. In such a case, the power supply voltage cannot be used as it is for the operating voltage within the LSI. Accordingly, the power supply voltage is stepped down once within the LSI, and then, supplied to the interior of the LSI.
Also, there is such a case that, in order to reduce the power consumption, the operating voltage within the LSI is intentionally reduced.
For that reason, a step-down circuit, which steps down the power supply voltage, is used.
For example, as shown in FIG. 9, there is a step-down circuit, which comprises an N channel type output transistor 101, a booster 102 for raising the gate voltage thereof, a voltage dividing circuit 103 including two resistors 103A and 103B of resistance values R1 and R2, a comparator 104, a clamp circuit 105 and a reference voltage generating device 106, and the step-down circuit is connected to a load circuit 107 (refer to, for example, Gerrit W. den Besten and Bram Nauta, “Embedded 5V-to-3.3V Voltage Regulator for Supplying Digital IC's in 3.3V CMOS Technology” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 7, JULY 1998). It is arranged so that clock signal is inputted to the booster 102 from a ring oscillator 108, and EN (enable) signal is inputted from the comparator 104.
In this step-down circuit, it is arranged so that the comparator 104 compares the divided voltage, which is the step-down output (step-down voltage) of the output transistor 101 divided by the voltage dividing circuit 103, with the reference voltage from the reference voltage generating device 106, and based on the comparison result, the operation of the booster 102 is controlled. And as shown in FIG. 10, when the output voltage (step-down output) of the step-down circuit is equal to or lower than a required voltage (target voltage), EN signal, which is outputted from the comparator 104, comes out as “H” (H level). Based on this, the booster 102 is caused to operate, and thus, the booster output, i.e., the gate voltage of the output transistor 101 is gradually raised. According to this, the step-down output also is gradually raised. On the other hand, when the output voltage of the step-down circuit becomes higher than a required voltage (target voltage), the EN signal outputted from the comparator 104 comes out as “L” (L level). Based on this, the operation of the booster 102 is stopped. After that, the booster output, i.e., the gate voltage of the output transistor 101 is maintained at a constant level, and thus, the step-down output is also maintained at a constant level. Since the step-down output is maintained at a constant level, the divided voltage, which is inputted to the inverting input terminal (−input terminal) of the comparator 104, is also maintained at a constant level.